The present disclosure relates to a memory element storing information based on any change of electrical characteristics observed in a memory layer including an ion source layer and a resistance change layer, and to a memory device.
A semiconductor nonvolatile memory popularly used for data storage has been a NOR or NAND flash memory. Such a semiconductor nonvolatile memory, however, has been pointed out that there are limitations on microfabrication considering the need for a high level of voltage for writing and erasing, and the limited number of electrons for injection to a floating gate.
For overcoming such limitations on microfabrication, a next-generation nonvolatile memory currently proposed is a resistance change memory such as ReRAM (Resistance Random Access Memory) or PRAM (Phase-Change Random Access Memory) (for example, see Japanese Unexamined Patent Application Publication No. 2009-164467). These memories are each in the simple configuration including a resistance change layer between two electrodes. In a memory of Japanese Unexamined Patent Application Publication No. 2009-43757, as an alternative to the resistance change layer, an ion source layer and an oxide film (thin film for storage) are provided between first and second electrodes.
The principles of resistance change in these resistance change memories are deemed to be based on the formation of a conductive path inside of the resistance change layer as a result of the movement of atoms or ions from the ion source layer to the resistance change layer by heat or an electric field, but the details thereof are not yet made clear. The currently leading theory is that the resistance value changes by the micro-migration of ions with oxidation reduction (for example, see Wei, Z. Kanazawa, et al. Electron Device Meeting, 2008. IEDM 2008. IEEE International). Moreover, with a resistance change memory element in which mobile ions are copper (Cu) in GeSe, a phenomenon of randomly-changing resistance is observed. There is a report about such a change of resistance, which is due to the thermal migration of mobile ions in a portion serving as a conductive path (for example, see Rainer Waser, et al. Advanced Materials 21, no. 25-26 (2009): 2632-2663).
The issue here is that the recent memory device is expected to be small in size and large in capacity. In order to meet such expectations, the capacity increase is aimed to be achieved by integration of a plurality of memory elements on a single chip.